Main Title |
Waste minimization assessment for a manufacturer producing printed circuit boards / |
Author |
Edwards, Harry W. ;
Kostrzewa, M. ;
Miller, P. S.
|
Other Authors |
|
CORP Author |
Colorado State Univ., Fort Collins. Dept. of Mechanical Engineering. ;University City Science Center, Philadelphia, PA.;Environmental Protection Agency, Cincinnati, OH. Risk Reduction Engineering Lab. |
Publisher |
U.S. Environmental Protection Agency, Risk Reduction Engineering Laboratory, |
Year Published |
1992 |
Report Number |
EPA/600-S-92-033; EPA-R-814903; PB93126621 |
Stock Number |
PB93-126621 |
OCLC Number |
26987664 |
Subjects |
Waste minimization--Research--Colorado ;
Printed circuits industry--Research--Colorado
|
Additional Subjects |
Waste management ;
Hazardous materials ;
Pollution abatement ;
Printed circuits ;
Manufacturing ;
Waste water ;
Plating ;
Photolithography ;
Water pollution control ;
Rinsing ;
Sludges ;
Electrowinning ;
Waste minimization ;
Source reduction ;
SIC 20-39
|
Internet Access |
|
Holdings |
Library |
Call Number |
Additional Info |
Location |
Last Modified |
Checkout Status |
EHAM |
TD793.9.E3 1992 |
|
Region 1 Library/Boston,MA |
04/29/2016 |
EJBD |
EPA 600-S-92-033 |
c.1 |
Headquarters Library/Washington,DC |
07/17/2013 |
EJED |
EPA 600/S-92/033 |
|
OCSPP Chemical Library/Washington,DC |
10/05/2001 |
ELBD ARCHIVE |
EPA 600-S-92-033 |
In Binder Received from HQ |
AWBERC Library/Cincinnati,OH |
10/04/2023 |
ELBD RPS |
EPA 600-S-92-033 |
repository copy |
AWBERC Library/Cincinnati,OH |
02/01/2016 |
EMBD |
EPA/600/S-92/033 |
|
NRMRL/GWERD Library/Ada,OK |
12/28/2001 |
NTIS |
PB93-126621 |
Some EPA libraries have a fiche copy filed under the call number shown. |
|
07/26/2022 |
|
Collation |
1 volume. |
Abstract |
The U.S. Environmental Protection Agency (EPA) has funded a pilot project to assist small- and medium-size manufacturers who want to minimize their generation of waste but who lack the expertise to do so. The WMAC team at Colorado State University performed an assessment at a plant which manufactures single-sided, double-sided, and multilayer printed circuit boards -- approximately 259,000 sq ft/yr. Circuit patterns are created on the boards and foil layers with a dry-film photoresist process and the multilayer boards are built up. The actual copper circuit pattern is generated by a series of photolithographic and plating processes. Final processing includes legend application, routing, rinsing, electrical testing, inspections, packing, and shipping. The team's report, detailing findings and recommendations, indicated that the majority of waste was generated in the plating lines and that the greatest savings could be obtained by installing a spray rinse and electrowinning system on the first rinse tank of the electrolytic copper plating line to reduce both copper plating rinse water (88 percent) and plating sludge (80 percent) due to drag-out in the first rinse tank. |
Notes |
Shipping list no.: 92-0605-P. "EPA/600-S-92-033 "Sept. 1992." |