1.0 Abstract -- 2.0 Introduction -- 3.0 Plant description -- 3.1. General -- 3.2. Chemical storage -- 3.3. Gas handling system -- 3.4. Monitoring system --4.0 Process descriptioin -- 5.0 Description of programs -- 5.1. Industrial hygiene -- 5.2. Education and training -- 5.3. Respirators and other personal protective equipment -- 5.4. Medical -- 5.5. Housekeeping -- 6.0 Sample data from preliminary or previous plant surveys -- 7.0 Description of control strategies for process operations of interest -- 7.1. Chemical vapor deposition -- 7.1.1. Engineering controls -- 7.1.2. Monitoring -- 7.1.3. Personal protective equipment -- 7.1.4. Work practices -- 7.2. Termal oxidation -- 7.3. Doping and hydrogen alloying -- 7.4. Wet chemical cleaning processes -- 7.5. Photolithography -- 7.6. Plasma etching -- 7.7. DC sputtering -- 7.8 Electron-beam evaporation -- 8.0 Conclusions and recommendations -- 9.0 References A preliminary control technology survey was conducted at Intel Corporation, Chandler, Arizona on August 12, 1981 by Battelle's Columbus Laboratories, Columbus, Ohio. The survey was conducted as part of a project under a U.S. Envrionmental Protection Agency contract funded through an Interagency Agreement with thte National Institute for Occupational Safety and Health. Intel Corporation manufacturers n-channel metal oxide semiconductor (N-MOS) integrated circuits. The Chandler facility opened in 1980 and is at less than half production capacity. The process operations in the manufacture of integrated circuits at Intel are contained within a Class 100 clean room. Particulate control is performed by filtration of inlet air through HEPA filters. Local air filtration is provided in the clean room by laminar flow benches with HEPA filtration. Process equipment is generally located in the laminar flow benches. Process operations employed at Intel Corporation in MOS integrated circuit manufacture include: 1) thermal oxidation of purchased pre-doped silicon wafers, 2) chemical vapor deposition of silicon nitride, polycrystalline silicon and silicon dioxide, 3) photolithographic processes for defining circuit paterns, including wafer cleaning, photoresist coating, soft-bake, projection mask alignment exposure, wafer developing, hard bake, plasma etching, and photoresist striping, 4) doping, including diffusion and ion implantatin, 5) hydrogen alloying, and 6) metalization, including electron beam evaporation and direct current (DC) sputtering.